Design and Implementation a 8 bits Pipeline Analog to Digital Converter in the Technology 0.6 μm CMOS Process

2008/08/04 by Eri Prasetyo, Prasetyo, Eri, Dominique Ginhac +3
Computer Science · Engineering · #Analog and Mixed-Signal Circuit Design #Computer Vision and Pattern Recognition (cs.CV) #FOS: Computer and information sciences #Robotics (cs.RO) #cs.CV #cs.RO

paper · pdf · doi:10.48550/arxiv.0808.0387

5 pages, Conference in Paris

arxiv created 2008/08/04 · openalex publication_date 2008/08/04 · arxiv updated 2009/12/01 · openalex created_date 2024/04/11 · openalex updated_date 2026/07/28

Abstract

This paper describes a 8 bits, 20 Msamples/s pipeline analog-to-digital converter implemented in 0.6 μm CMOS technology with a total power dissipation of 75.47 mW. Circuit techniques used include a precise comparator, operational amplifier and clock management. A switched capacitor is used to sample and multiplying at each stage. Simulation a worst case DNL and INL of 0.75 LSB. The design operate at 5 V dc. The ADC achieves a SNDR of 44.86 dB. keywords : pipeline, switched capacitor, clock management

Related

• A full-custom ASIC design of a 8-bit, 25 MHz, Pipeline ADC using 0.35 um CMOS technology
• A Low-Power 9-bit Pipelined CMOS ADC with Amplifier and Comparator Sharing Technique
• Analog-to-digital converter survey and analysis
• 1.5 bit-per-stage 8-bit Pipelined CMOS A/D Converter for Neuromophic Vision Processor
• A 31-μ W, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS