2010/11/18 by Moslem Rashidi, Rashidi, Moslem, Mikael Hogrud +8
Computer Science · Engineering · #Advancements in Semiconductor Devices and Circuit Design #Analog and Mixed-Signal Circuit Design #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Low-power high-performance VLSI design #cs.AR
paper · pdf · doi:10.48550/arxiv.1011.4157
the paper needs to be withdrawn because of copyright conflicts
openalex publication_date 2010/11/18 · arxiv created 2012/07/24 · arxiv updated 2012/07/25 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
The purpose of this project was to design and implement a pipeline Analog-to-Digital Converter using 0.35um CMOS technology. Initial requirements of a 25-MHz conversion rate and 8-bits of resolution where the only given ones. Although additional secondary goals such as low power consumption and small area were stated. The architecture is based on a 1.5 bit per stage structure utilizing digital correction for each stage [12]. A differential switched capacitor circuit consisting of a cascade gm-C op-amp with 200MHz ft is used for sampling and amplification in each stage [12]. Differential dynamic comparators are used to implement the decision levels required for the 1.5-b per stage structure. Correction of the pipeline is accomplished by using digital correction circuit consist of D-latches and full-adders. Area and Power consumption of whole design was 0.24mm2 and 35mW respectively. The maximum sample rate at which the converter gave an adequate output was 33MHz.