Implementation and Applications of a Ternary Threshold Logic Gate

2022/11/22 by Ahmet Unutulmaz, Unutulmaz, Ahmet, Cem Ünsalan +1
Computer Science · Engineering · #Advanced Memory and Neural Computing #FOS: Electrical engineering #Low-power high-performance VLSI design #Quantum Computing Algorithms and Architecture #Signal Processing (eess.SP) #electronic engineering #information engineering

paper · pdf · doi:10.48550/arxiv.2211.12176

openalex publication_date 2022/11/22 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28

Abstract

Reducing delay, power consumption, and chip area of a logic circuit are the main targets of a designer. Most of the times, the designer sacrifices power consumption and chip area to improve delay for a given technology node. To overcome this problem, we propose a ternary threshold logic gate. We implement the proposed gate by combining threshold logic and ternary logic. Then, we construct basic building blocks of a ternary ALU (as logic gates, comparator, and arithmetic circuits) using the proposed gate. We show that the proposed ternary TLG improves delay, power consumption, and chip area of ternary circuits via simulations. Thus, the proposed gate can be used to improve delay, power consumption, and chip area of ternary circuits.

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