2013/08/08 by Mrigank Sharad, Sharad, Mrigank, Deliang Fan +3 · 1 citation
Engineering · #Advanced Memory and Neural Computing #Disordered Systems and Neural Networks (cond-mat.dis-nn) #Emerging Technologies (cs.ET) #FOS: Computer and information sciences #FOS: Physical sciences #Ferroelectric and Negative Capacitance Devices #Hardware Architecture (cs.AR) #Semiconductor materials and devices
paper · pdf · doi:10.48550/arxiv.1308.4672
openalex publication_date 2013/08/08 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
We propose dynamic resistive threshold-logic (DRTL) design based on non-volatile resistive memory. A threshold logic gate (TLG) performs summation of multiple inputs multiplied by a fixed set of weights and compares the sum with a threshold. DRTL employs resistive memory elements to implement the weights and the thresholds, while a compact dynamic CMOS latch is used for the comparison operation. The resulting DRTL gate acts as a low-power, configurable dynamic logic unit and can be used to build fully pipelined, high-performance programmable computing blocks. Multiple stages in such a DRTL design can be connected using energy-efficient low swing programmable interconnect networks based on resistive switches. Owing to memory-based compact logic and interconnect design and highspeed dynamic-pipelined operation, DRTL can achieve more than two orders of magnitude improvement in energy-delay product as compared to look-up table based CMOS FPGA.