2023/05/06 by Kawashima, Ichiro
#FOS: Computer and information sciences #Logic in Computer Science (cs.LO)
paper · doi:10.48550/arxiv.2305.04115
Ternary logic is expected to increase the area efficiency of VLSI due to its expressiveness compared to the traditional binary logic. This paper proposes a new symmetric ternary logic and a systematic logic composition methodology that enables us to design any ternary logic circuits. The methodology is demonstrated by implementing the ternary inverters, ternary NAND, ternary NOR, and ternary half-adder operators with the proposed symmetric ternary operators.