2022/09/06 by M.A. Benkechkache, Benkechkache, Mohamed El Amine, Saϊda Latreche +3
Engineering · #3D IC and TSV technologies #Additive Manufacturing and 3D Printing Technologies #Electronic Packaging and Soldering Technologies #FOS: Physical sciences #Instrumentation and Detectors (physics.ins-det)
paper · pdf · doi:10.48550/arxiv.2209.02230
openalex publication_date 2022/09/06 · openalex created_date 2022/09/08 · openalex updated_date 2026/07/28
The semiconductor industry's rapid advancement pushes conventional two-dimensional technology to its utmost limitations in terms of scaling, performance, and cost factors. These challenges drive the usage of 3D technology in the production of various Integrated Circuits. One of the numerous features of 3D Integration is the use of Through Silicon Vias (TSVs) for the assembly of multilayers into a single stack. This process, which was initially developed for memory chips, has been used afterward in many applications in other areas of microelectronics. The purpose of this research is to assess the effect of 3D-TSV interconnection on the performance of MOS transistors and CMOS circuits. This is accomplished using numerical and analytical models capable of describing the substrate coupling induced by TSV at the circuit level. The analytical approach proposed enables the study and optimization of the performance, not only of MOS devices but also large CMOS circuits with 3D interconnects as a function of various technological and electrical parameters.