2018/03/18 by Jan Gray, Aaron Smith, Gray, Jan +2 · 3 voices
Computer Science · #Embedded Systems Design Techniques #Interconnection Networks and Systems #Parallel Computing and Optimization Techniques #cs.AR
paper · pdf · doi:10.48550/arxiv.1803.06617
openalex publication_date 2018/03/18 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
In-order scalar RISC architectures have been the dominant paradigm in FPGA\nsoft processor design for twenty years. Prior out-of-order superscalar\nimplementations have not exhibited competitive area or absolute performance.\nThis paper describes a new way to build fast and area-efficient out-of-order\nsuperscalar soft processors by utilizing an Explicit Data Graph Execution\n(EDGE) instruction set architecture. By carefully mapping the EDGE\nmicroarchitecture, and in particular, its dataflow instruction scheduler, we\ndemonstrate the feasibility of an out-of-order FPGA architecture. Two scheduler\ndesign alternatives are compared.\n