2011/10/17 by Jorge Luiz e Silva, Joelmir José Lopes, Silva, Jorge Luiz e +5
Computer Science · #Embedded Systems Design Techniques #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Interconnection Networks and Systems #Parallel Computing and Optimization Techniques
paper · pdf · doi:10.48550/arxiv.1110.3655
openalex publication_date 2011/10/17 · openalex created_date 2022/10/01 · openalex updated_date 2026/07/28
In this paper, the acceleration of algorithms using a design of a field programmable gate array (FPGA) as a prototype of a static dataflow architecture is discussed. The static dataflow architecture using operators interconnected by parallel buses was implemented. Accelerating algorithms using a dataflow graph in a reconfigurable system shows the potential for high computation rates. The results of benchmarks implemented using the static dataflow architecture are reported at the end of this paper.