2020/08/10 by Sumit K. Mandal, Mandal, Sumit K., Anish Krishnakumar +7
Computer Science · Engineering · Materials Science · #Advancements in Battery Materials #FOS: Computer and information sciences #Interconnection Networks and Systems #Performance (cs.PF) #Supercapacitor Materials and Fabrication
paper · pdf · doi:10.48550/arxiv.2008.03904
openalex publication_date 2020/08/10 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
Priority-aware networks-on-chip (NoCs) are used in industry to achieve\npredictable latency under different workload conditions. These NoCs incorporate\ndeflection routing to minimize queuing resources within routers and achieve low\nlatency during low traffic load. However, deflected packets can exacerbate\ncongestion during high traffic load since they consume the NoC bandwidth.\nState-of-the-art analytical models for priority-aware NoCs ignore deflected\ntraffic despite its significant latency impact during congestion. This paper\nproposes a novel analytical approach to estimate end-to-end latency of\npriority-aware NoCs with deflection routing under bursty and heavy traffic\nscenarios. Experimental evaluations show that the proposed technique\noutperforms alternative approaches and estimates the average latency for real\napplications with less than 8% error compared to cycle-accurate simulations.\n