Analytical Performance Modeling of NoCs under Priority Arbitration and\n Bursty Traffic

2020/07/27 by Sumit K. Mandal, Mandal, Sumit K., Raid Ayoub +7
Computer Science · Engineering · #Advanced Memory and Neural Computing #Advancements in Battery Materials #FOS: Computer and information sciences #Interconnection Networks and Systems #Performance (cs.PF)

paper · pdf · doi:10.48550/arxiv.2007.13951

openalex publication_date 2020/07/27 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28

Abstract

Networks-on-Chip (NoCs) used in commercial many-core processors typically\nincorporate priority arbitration. Moreover, they experience bursty traffic due\nto application workloads. However, most state-of-the-art NoC analytical\nperformance analysis techniques assume fair arbitration and simple traffic\nmodels. To address these limitations, we propose an analytical modeling\ntechnique for priority-aware NoCs under bursty traffic. Experimental\nevaluations with synthetic and bursty traffic show that the proposed approach\nhas less than 10% modeling error with respect to cycle-accurate NoC simulator.\n

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