A protocol to reduce worst-case latency in deflection-based on-chip networks

2025/10/13 by Indrusiak, Leandro Soares
#FOS: Computer and information sciences #Networking and Internet Architecture (cs.NI) #Performance (cs.PF)

paper · doi:10.48550/arxiv.2510.11361

Abstract

We present a novel protocol that reduces worst-case packet latency in deflection-based on-chip interconnect networks. It enforces the deflection of the header of a packet but not its payload, resulting in a reduction in overall network traffic and, more importantly, worst-case packet latency due to decreased pre-injection latency.

Citations

• Real-Time Guarantees in Routerless Networks-on-Chip

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