2024/06/01 by Akshay Karkal Kamath, Kamath, Akshay Karkal, Bharath Kumar +11
Computer Science · Social Sciences · #Energy and Environmental Systems #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Internet of Things and Social Network Interactions #Technology and Data Analysis
paper · pdf · doi:10.48550/arxiv.2406.00542
openalex publication_date 2024/06/01 · openalex created_date 2024/06/06 · openalex updated_date 2026/07/28
The development of a standard cell library involves characterization of a number of gate-level circuits at various cell-level abstractions. Verifying the behavior of these cells largely depends on the manual skills of the circuit designers. Especially challenging are the power management and data retention cells which must be checked thoroughly for voltage and power configurations in addition to their logic functionality. Also, when standard cells are extracted into various models, any inconsistencies in these models typically goes unchecked during library development. Thus, validating these cells exhaustively prior to customer delivery is highly advantageous to not only improve customer satisfaction but also to reduce design costs. We address this challenge by presenting a methodology to validate the power management and data retention cells that are used in the logical design flow of low-power chips. For a quick adoption by standard cell library design teams, the framework is fully automated and runs out-of-the-box. The proposed framework has been implemented and deployed within the Samsung Foundry ecosystem to enhance the overall quality of library design kit deliverables.