2018/05/28 by Yongfu Li, Li, Yongfu, Wan Chia Ang +9 · 1 citation
Computer Science · Engineering · #Advanced Data Storage Technologies #Experimental Learning in Engineering #FOS: Computer and information sciences #Manufacturing Process and Optimization #Other Computer Science (cs.OH) #cs.OH
paper · pdf · doi:10.48550/arxiv.1805.10745
Synopsys User Group Silicon Valley (SNUG) 2017
arxiv created 2018/05/28 · openalex publication_date 2018/05/28 · arxiv updated 2018/05/29 · openalex created_date 2018/06/01 · openalex updated_date 2026/07/28
Starting from 22-nm, a standard cell must be designed to be full lithography-compliant, which includes Design Rule Check, Design-for-Manufacturability and Double-Patterning compliant. It has become a great challenge for physical layout designers to provide a full lithography-compliant standard cell layout that is optimized for area, power, timing, signal integrity, and yield. This challenge is further exacerbated with abutted single- and multiple-height standard cells. At present, different foundries and library vendors have different approaches for full lithography-compliant library preparation and validation. To the best of our knowledge, there is no single tool integrates all types of lithography-compliant check in standard cell libraries validation flow. In this work, we will demonstrate multiple lithography-compliant verification for standard cell library development flow. Validation flow and detailed algorithm implementation will be explained to assist engineers to achieve full lithography-compliant standard cell libraries. An area-efficient standard cell placement methodology will also be discussed to validate the issues arises from standard cell abutment.