2020/05/08 by Hadi Mardani Kamali, Kimia Zamiri Azar, Kamali, Hadi Mardani +5
Computer Science · Engineering · #Physical Unclonable Functions (PUFs) and Hardware Security #Integrated Circuits and Semiconductor Failure Analysis #VLSI and Analog Circuit Testing
paper · pdf · doi:10.48550/arxiv.2005.04262
In this paper, we assess the security and testability of the state-of-the-art\ndesign-for-security (DFS) architectures in the presence of scan-chain\nlocking/obfuscation, a group of solution that has previously proposed to\nrestrict unauthorized access to the scan chain. We discuss the key leakage\nvulnerability in the recently published prior-art DFS architectures. This\nleakage relies on the potential glitches in the DFS architecture that could\nlead the adversary to make a leakage condition in the circuit. Also, we\ndemonstrate that the state-of-the-art DFS architectures impose some substantial\narchitectural drawbacks that moderately affect both test flow and design\nconstraints. We propose a new DFS architecture for building a secure scan chain\narchitecture while addressing the potential of key leakage. The proposed\narchitecture allows the designer to perform the structural test with no\nlimitation, enabling an untrusted foundry to utilize the scan chain for\nmanufacturing fault testing without needing to access the scan chain. Our\nproposed solution poses negligible limitation/overhead on the test flow, as\nwell as the design criteria.\n