2019/02/01 by Mostafa Ayesh, Ayesh, Mostafa, Sameh Ibrahim +3
Engineering · #FOS: Electrical engineering #Signal Processing (eess.SP) #eess.SP #electronic engineering #information engineering
paper · pdf · doi:10.48550/arxiv.1902.00233
9 pages, Journal, 5 Tables, 19 Figures
arxiv created 2019/02/01 · arxiv updated 2019/02/04
This paper presents a discrete-time analog frontend for an analog-to-digital (ADC) based equalizers. The frontend uses a discrete-time linear equalizer (DTLE) and ultralow-power 4-bit time-interleaved charge-steering flash ADC. The DTLE serves two functions; linear equalization and sampling and holding for the following charge-steering ADC. The ADC uses fully differential low-power clocked comparators. Low power in the comparators is achieved by embedding a dynamic latch into the core of a charge-steering pre-amplifier. The 20-Gb/s front-end is designed and simulated in 65-nm CMOS technology. The flash ADC uses 4-stage interleaving and thus requires 4 DTLEs running at 5 Gb/s. A 5-Gb/s DTLE consumes 0.57 mW from a 1.2-V supply and the ADC consumes 15.5 mW from a 1-V supply at 20 GS/s for a total power dissipation of 17.78 mW or 0.89 pJ/bit. The ADC has an SNDR of 23.9 dB, an SFDR of 33.6 dB, and an effective number of bits (ENOB) of 3.67 bits for a sinusoidal input of frequency 9.84 GHz and amplitude 600 mVdiff .