2017/02/20 by Yixing Li, Li, Yixing, Zichuan Liu +7
Computer Science · Engineering · #Advanced Memory and Neural Computing #Advanced Neural Network Applications #C.3 #Computer Vision and Pattern Recognition (cs.CV) #Distributed #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Machine Learning (cs.LG) #Machine Learning and ELM #Parallel #and Cluster Computing (cs.DC) #cs.AR #cs.CV #cs.DC #cs.LG
paper · pdf · doi:10.48550/arxiv.1702.06392
openalex publication_date 2017/02/20 · arxiv created 2017/06/08 · arxiv updated 2017/06/09 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
FPGA-based hardware accelerators for convolutional neural networks (CNNs) have obtained great attentions due to their higher energy efficiency than GPUs. However, it is challenging for FPGA-based solutions to achieve a higher throughput than GPU counterparts. In this paper, we demonstrate that FPGA acceleration can be a superior solution in terms of both throughput and energy efficiency when a CNN is trained with binary constraints on weights and activations. Specifically, we propose an optimized FPGA accelerator architecture tailored for bitwise convolution and normalization that features massive spatial parallelism with deep pipelines stages. A key advantage of the FPGA accelerator is that its performance is insensitive to data batch size, while the performance of GPU acceleration varies largely depending on the batch size of the data. Experiment results show that the proposed accelerator architecture for binary CNNs running on a Virtex-7 FPGA is 8.3x faster and 75x more energy-efficient than a Titan X GPU for processing online individual requests in small batch sizes. For processing static data in large batch sizes, the proposed solution is on a par with a Titan X GPU in terms of throughput while delivering 9.5x higher energy efficiency.