Modeling and Simulation of Electromigration Behavior for Via Array Structure

2018/01/25 by Karthik Airani, Airani, Karthik, Rohit Guttal +1
Engineering · Materials Science · #Applied Physics (physics.app-ph) #Copper Interconnects and Reliability #Electronic Packaging and Soldering Technologies #FOS: Physical sciences #Semiconductor materials and devices

paper · pdf · doi:10.48550/arxiv.1801.08281

openalex publication_date 2018/01/25 · openalex created_date 2018/02/02 · openalex updated_date 2026/07/28

Abstract

In this paper, we develop a analytical model and algorithm for calculating uneven current distribution in via array structures. We propose a stress time translation formula and cumulative failure distribution equation to model the memory effect of electro migration stress or damage on a via array structure. We develop a method to project via array electromigration (EM) lifetime based on an arbitrary via failure sequence, and demonstrate that the proposed via array EM lifetime distribution trend correlates well with experimental results.

Citations

• Customized Routing Optimization Based on Gradient Boost Regressor Model

Related

• Chip-Level Electromigration Reliability Evaluation with Multiple On-Die Variation Effects
• A Linear-Time Algorithm for Steady-State Analysis of Electromigration in General Interconnects
• Uneven Current Distribution Modeling and Random Walk based Variation\n Analysis for interconnect Electromigration Estimation
• Electromigration-Aware Architecture for Modern Microprocessors
• A New, Computationally Efficient "Blech Criterion" for Immortality in General Interconnects