LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines

2024/06/24 by Jitendra Bhandari, Johann Knechtel, Bhandari, Jitendra +7 · 1 voice · 4 citations
Computer Science · Engineering · #Parallel Computing and Optimization Techniques #Real-time simulation and control systems #VLSI and Analog Circuit Testing #cs.AR

paper · pdf · doi:10.48550/arxiv.2406.17132

arxiv published 2024/06/24 · arxiv updated 2025/06/21

Abstract

This work investigates the potential of tailoring Large Language Models (LLMs), specifically GPT3.5 and GPT4, for the domain of chip testing. A key aspect of chip design is functional testing, which relies on testbenches to evaluate the functionality and coverage of Register-Transfer Level (RTL) designs. We aim to enhance testbench generation by incorporating feedback from commercial-grade Electronic Design Automation (EDA) tools into LLMs. Through iterative feedback from these tools, we refine the testbenches to achieve improved test coverage. Our case studies present promising results, demonstrating that this approach can effectively enhance test coverage. By integrating EDA tool feedback, the generated testbenches become more accurate in identifying potential issues in the RTL design. Furthermore, we extended our study to use this enhanced test coverage framework for detecting bugs in the RTL implementations

Cited by

• AutoFSM: A Multi-agent Framework for FSM Code Generation with IR and SystemC-Based Testing
• SAGE-HLS: Syntax-Aware AST-Guided LLM for High-Level Synthesis Code Generation
• Legal Document Summarization: Enhancing Judicial Efficiency through Automation Detection
• SALAD: Systematic Assessment of Machine Unlearning on LLM-Aided Hardware Design

Discussions

• arxiv 📄 LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines http://arxiv.org/abs/2406.17132v1 This work investigates the potential of tailoring Large Language Models (LLMs) [bsky, 0 points, 0 comments]

Related

• AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design
• CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design
• LLM4DV: Using Large Language Models for Hardware Test Stimuli Generation
• LLM-Aided Efficient Hardware Design Automation
• FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification