2003/12/22 by H. Ando, Yoshitoku Yoshida, Akira Inoue +11 · 38 citations
Computer Science · Engineering · #Interconnection Networks and Systems #Parallel Computing and Optimization Techniques #Embedded Systems Design Techniques #Microprocessor #Computer science #Electrical engineering #Computer hardware #Engineering
paper · doi:10.1109/isscc.2003.1234286
openalex publication_date 2003/12/22 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/29
A fifth generation SPARC64 processor implemented in 130 nm CMOS process with 8 layers of Cu metallization operates with a 1.3 GHz clock and dissipates 34.7 W. The processor is a 4-issue out-of-order design with 2 MB on-chip level-2 cache. Error checking is added on the data-path in addition to memory. An instruction is retried for correction when an error is detected in the datapath.