2024/02/14 by Komala Krishna, Nandakumar Nambath · 6 citations
Computer Science · Engineering · #Advancements in PLL and VCO Technologies #Analog and Mixed-Signal Circuit Design #CMOS #Comparator #Computer science #Converters #Delta-sigma modulation #Electrical engineering #Electronic engineering #Engineering #VLSI and Analog Circuit Testing #Voltage
paper · doi:10.1142/s021812662430006x
published in Journal of Circuits Systems and Computers 33(13) (World Scientific)
openalex publication_date 2024/02/14 · crossref created 2024/02/14 · crossref issued 2024/03/14 · crossref published 2024/03/14 · crossref published-online 2024/03/14 · crossref deposited 2024/08/07 · crossref published-print 2024/09/15 · openalex created_date 2025/10/10 · crossref indexed 2026/08/05 · openalex updated_date 2026/08/06
This paper presents a comprehensive review of the state-of-art high-speed dynamic comparators. The comparator is a critical block of high-speed, low-power analog-to-digital converters, determining the speed and overall power consumption. Therefore, the design of a high-speed comparator with tolerable offset, noise and power consumption is of utmost importance. Recent work reported on high-speed comparator topologies is investigated in detail with the help of simulations in 65[Formula: see text]nm CMOS technology. Various parameters, such as delay, energy consumption, speed, offset, kickback noise, power delay product, etc., are compared. A detailed comparative study is also presented on several design methodologies.