2017/12/31 by Amogh Agrawal, Akhilesh Jaiswal, Chankyu Lee +1 · 312 citations
Computer Science · Engineering · Mathematics · #Advanced Memory and Neural Computing #Algorithm #Boolean circuit #Boolean function #Bottleneck #Circuit minimization for Boolean functions #Computer hardware #Computer science #Embedded system #Ferroelectric and Negative Capacitance Devices #Mathematics #Overhead (engineering) #Parallel computing #Semiconductor materials and devices #Static random-access memory #Theoretical computer science #Topology (electrical circuits) #Von Neumann architecture #cs.ET
paper · pdf · doi:10.1109/tcsi.2018.2848999
published in IEEE Transactions on Circuits and Systems I Regular Papers 65(12), 4219-4232 (Institute of Electrical and Electronics Engineers) · This article has been accepted in a future issue of IEEE Transactions on Circuits and Systems-I: Regular Papers
openalex created_date 2017/12/22 · arxiv created 2018/06/18 · openalex publication_date 2018/07/02 · arxiv updated 2018/10/23 · openalex updated_date 2026/08/05
Silicon-based static random access memories (SRAM) and digital Boolean logic have been the workhorse of the state-of-the-art computing platforms. Despite tremendous strides in scaling the ubiquitous metal-oxide-semiconductor transistor, the underlying von-Neumann computing architecture has remained unchanged. The limited throughput and energy-efficiency of the state-of-the-art computing systems, to a large extent, result from the well-known von-Neumann bottleneck. The energy and throughput inefficiency of the von-Neumann machines have been accentuated in recent times due to the present emphasis on data-intensive applications such as artificial intelligence, machine learning, and cryptography. A possible approach towards mitigating the overhead associated with the von-Neumann bottleneck is to enable in-memory Boolean computations. In this paper, we present an augmented version of the conventional SRAM bit-cells, called the X-SRAM, with the ability to perform in-memory, vector Boolean computations, in addition to the usual memory storage operations. We propose at least six different schemes for enabling in-memory vector computations, including NAND, NOR, IMP (implication), XOR logic gates, with respect to different bit-cell topologies - the 8T cell and the 8+T Differential cell. In addition, we also present a novel `read-compute-store' scheme, wherein the computed Boolean function can be directly stored in the memory without the need of latching the data and carrying out a subsequent write operation. The feasibility of the proposed schemes has been verified using the predictive transistor models and detailed Monte-Carlo variation analysis. As an illustration, we also present the efficacy of the proposed in-memory computations by implementing advanced encryption standard algorithm on a non-standard von-Neumann machine wherein the conventional SRAM is replaced by X-SRAM. Our simulations indicated that up to 75% of memory accesses can be saved using the proposed techniques.