2015/11/30 by YouZhe Fan, ChenYang Xia, Ji Chen +4 · 58 citations
Biochemistry, Genetics and Molecular Biology · Computer Science · Engineering · Mathematics · #Advanced Wireless Communication Techniques #Algorithm #Block code #Computer engineering #Computer hardware #Computer science #Concatenated error correction code #DNA and Biological Computing #Decoding methods #Error Correcting Code Techniques #Latency (audio) #List decoding #Parallel computing #Telecommunications #Thresholding #cs.AR #cs.IT #eess.SP #math.IT
paper · pdf · doi:10.1109/jsac.2015.2504318
published in IEEE Journal on Selected Areas in Communications 34(2), 303-317 (Institute of Electrical and Electronics Engineers) · 15 pages, 13 figures, 5 tables
openalex publication_date 2015/11/30 · arxiv created 2018/06/29 · arxiv updated 2018/07/02 · openalex created_date 2020/11/23 · openalex updated_date 2026/08/05
Due to their provably capacity-achieving performance, polar codes have attracted a lot of research interest recently. For a good error-correcting performance, list successive-cancellation decoding (LSCD) with large list size is used to decode polar codes. However, as the complexity and delay of the list management operation rapidly increase with the list size, the overall latency of LSCD becomes large and limits the applicability of polar codes in high-throughput and latency-sensitive applications. Therefore, in this work, the low-latency implementation for LSCD with large list size is studied. Specifically, at the system level, a selective expansion method is proposed such that some of the reliable bits are not expanded to reduce the computation and latency. At the algorithmic level, a double thresholding scheme is proposed as a fast approximate-sorting method for the list management operation to reduce the LSCD latency for large list size. A VLSI architecture of the LSCD implementing the selective expansion and double thresholding scheme is then developed, and implemented using a UMC 90 nm CMOS technology. Experimental results show that, even for a large list size of 16, the proposed LSCD achieves a decoding throughput of 460 Mbps at a clock frequency of 658 MHz.