1998/01/01 by İlker Hamzaoğlu, J.H. Patel · 2 citations
Computer Science · Engineering · #VLSI and Analog Circuit Testing #Low-power high-performance VLSI design #Integrated Circuits and Semiconductor Failure Analysis #Computer science #Algorithm #Citation #Combinational logic #Test (biology) #Center (category theory) #Research center #Library science #Logic gate
paper · pdf · doi:10.1145/288548.288615
openalex publication_date 1998/01/01 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/29
Thispaperpresents two new algorithms, Redundant Vec-torElimination (RVE) and Essential Fault Reduction (EFR), for generating compact test sets for combinational circuits under the single stuck at fault model, and a new heuristic for estimating ihe minimum single stuck at fault test set size. 7hese algon.thms together with the dynamic compaction algorithm are incorporated into an advancedATPG systemfor combinational circuits, called MinTest. MinTestfound better lower bounds and generated smaller test sets than the previ-OUSIJY published resultsfor the ISCAS85 andfill scan version of the ISCAS89 benchmark circuits.