1987/01/01 by J. Yetter, M. Forsyth, W.S. Jaffe +2 · 1 citation
Computer Science · Engineering · #Parallel Computing and Optimization Techniques #Low-power high-performance VLSI design #VLSI and FPGA Design Techniques
paper · doi:10.1109/isscc.1987.1157220
openalex publication_date 1987/01/01 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/29
A Reduced Instruction Set Computer using direct hardware instruction decode and 3-stage pipelined execution will be described. At an operating frequency of 30MHz, a 120Mbytes/s transfer rate on an external cache/coprocessor interface is achieved. NMOS technology is used to implement 115K transistors on an 8.4mm square chip.