2011/12/19 by Pia Juliane Wessely, Frank Wessely, Emrah Birinci +2 · 29 citations
Engineering · Materials Science · Physics and Astronomy · #Bilayer graphene #Chemical vapor deposition #Electrical engineering #Field-effect transistor #Graphene #Graphene and Nanomaterials Applications #Graphene foam #Graphene nanoribbons #Graphene oxide paper #Graphene research and applications #Materials science #Monolayer #Nanotechnology #Nanowire Synthesis and Applications #Optoelectronics #Raman spectroscopy #Silicon #Substrate (aquarium) #Transistor #Wafer #cond-mat.mes-hall
paper · pdf · doi:10.1116/1.4711128
published in Journal of Vacuum Science & Technology B Nanotechnology and Microelectronics Materials Processing Measurement and Phenomena 30(3) · 15 pages, 4 figures
arxiv created 2011/12/19 · openalex publication_date 2012/05/01 · arxiv updated 2012/05/23 · openalex created_date 2025/10/10 · openalex updated_date 2026/08/05
The authors invented a method to fabricate graphene transistors on oxidized silicon wafers without the need to transfer graphene layers. To stimulate the growth of graphene layers on oxidized silicon, a catalyst system of nanometer thin aluminum/nickel double layer is used. This catalyst system is structured via liftoff before the wafer enters the catalytic chemical vapor deposition (CCVD) chamber. In the subsequent methane-based growth process, monolayer graphene field-effect transistors and bilayer graphene field-effect transistors are realized directly on oxidized silicon substrate, whereby the number of stacked graphene layers is determined by the selected CCVD process parameters, e.g., temperature and gas mixture. Subsequently, Raman spectroscopy is performed within the channel region in between the catalytic areas and the Raman spectra of five-layer, bilayer, and monolayer graphene confirm the existence of graphene grown by this silicon-compatible, transfer-free and in situ fabrication approach. These graphene FETs will allow a simple and low-cost integration of graphene devices for nanoelectronic applications in a hybrid silicon CMOS environment.