CVA6S+: A Superscalar RISC-V Core with High-Throughput Memory Architecture

2025/04/20 by Riccardo Tedeschi, Tedeschi, Riccardo, Gianmarco Ottavi +25 · 1 citation
Computer Science · #Embedded Systems Design Techniques #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Parallel Computing and Optimization Techniques #Real-Time Systems Scheduling

paper · pdf · doi:10.48550/arxiv.2505.03762

openalex publication_date 2025/04/20 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28

Abstract

Open-source RISC-V cores are increasingly adopted in high-end embedded domains such as automotive, where maximizing instructions per cycle (IPC) is becoming critical. Building on the industry-supported open-source CVA6 core and its superscalar variant, CVA6S, we introduce CVA6S+, an enhanced version incorporating improved branch prediction, register renaming and enhanced operand forwarding. These optimizations enable CVA6S+ to achieve a 43.5% performance improvement over the scalar configuration and 10.9% over CVA6S, with an area overhead of just 9.30% over the scalar core (CVA6). Furthermore, we integrate CVA6S+ with the OpenHW Core-V High-Performance L1 Dcache (HPDCache) and report a 74.1% bandwidth improvement over the legacy CVA6 cache subsystem.

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