Efficient Trace for RISC-V: Design, Evaluation, and Integration in CVA6

2025/03/24 by Umberto Laghi, Simone Manoni, Laghi, Umberto +5
Computer Science · Engineering · Physics and Astronomy · #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Parallel Computing and Optimization Techniques #Particle Detector Development and Performance #Radiation Effects in Electronics

paper · pdf · doi:10.48550/arxiv.2504.01972

openalex publication_date 2025/03/24 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28

Abstract

In this work, we present the design and evaluation of a Processor Tracing System compliant with the RISC-V Efficient Trace specification for Instruction Branch Tracing. We integrate our system into the host domain of a state-of-the-art edge architecture based on CVA6. The proposed Tracing System introduces a total overhead of 9.2% in terms of resource utilization on a Xilinx VCU118 FPGA on the CVA6 subsystem while achieving an average compression rate of 95.1% on platform-specific tests, compared to tracing each full opcode instruction.

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