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Performance of a spin-based insulated gate field effect transistor

2006/03/09 by Kimberley C. Hall, Michael E. Flatté · 2 citations
Engineering · Physics and Astronomy · #Advancements in Semiconductor Devices and Circuit Design #Quantum and electron transport phenomena #Semiconductor materials and devices #cond-mat.mes-hall #cond-mat.mtrl-sci

paper · pdf · doi:10.1063/1.2192152

published as Appl. Phys. Lett. 88, 162503 (2006). · 4 pages including 3 figures, APL in press

arxiv created 2006/03/09 · openalex publication_date 2006/04/17 · arxiv updated 2009/12/01 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28

Abstract

Fundamental physical properties limiting the performance of spin field effect transistors are compared to those of ordinary (charge-based) field effect transistors. Instead of raising and lowering a barrier to current flow these spin transistors use static spin-selective barriers and gate control of spin relaxation. The different origins of transistor action lead to distinct size dependences of the power dissipation in these transistors and permit sufficiently small spin-based transistors to surpass the performance of charge-based transistors at room temperature or above. This includes lower threshold voltages, smaller gate capacitances, reduced gate switching energies, and smaller source-drain leakage currents.

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