2013/06/23 by Harold W. Cain, Maged M. Michael, Brad Frey +3 · 3 citations
Computer Science · #Advanced Data Storage Technologies #Distributed systems and fault tolerance #Parallel Computing and Optimization Techniques
paper · doi:10.1145/2485922.2485942
openalex publication_date 2013/06/23 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/29
On the twentieth anniversary of the original publication [10], following ten years of intense activity in the research literature, hardware support for transactional memory (TM) has finally become a commercial reality, with HTM-enabled chips currently or soon-to-be available from many hardware vendors. In this paper we describe architectural support for TM added to a future version of the Power ISA™. Two imperatives drove the development: the desire to complement our weakly-consistent memory model with a more friendly interface to simplify the development and porting of multithreaded applications, and the need for robustness beyond that of some early implementations. In the process of commercializing the feature, we had to resolve some previously unexplored interactions between TM and existing features of the ISA, for example translation shootdown, interrupt handling, atomic read-modify-write primitives, and our weakly consistent memory model. We describe these interactions, the overall architecture, and discuss the motivation and rationale for our choices of architectural semantics, beyond what is typically found in reference manuals.