Early experience with a commercial hardware transactional memory implementation

2009/03/07 by Dave Dice, Yossi Lev, Mark Moir +1 · 4 citations
Computer Science · Psychology · #Distributed systems and fault tolerance #Advanced Data Storage Technologies #Cognitive Functions and Memory

paper · doi:10.1145/1508244.1508263

openalex publication_date 2009/03/07 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/29

Abstract

We report on our experience with the hardware transactional memory (HTM) feature of two revisions of a prototype multicore processor. Our experience includes a number of promising results using HTM to improve performance in a variety of contexts, and also identifies some ways in which the feature could be improved to make it even better. We give detailed accounts of our experiences, sharing techniques we used to achieve the results we have, as well as describing challenges we faced in doing so. This technical report expands on our ASPLOS paper [9], providing more detail and reporting on additional work conducted since that paper was written.

Citations

• DCAS is not a silver bullet for nonblocking algorithm design

Cited by

• Robust architectural support for transactional memory in the power architecture
• Compare-and-swap [wikipedia]
• Double compare-and-swap [wikipedia]
• Transactional memory [wikipedia]

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