2D Semiconductor FETs—Projections and Design for Sub-10 nm VLSI

2015/09/15 by Wei Cao, Jiahao Kang, Deblina Sarkar +2 · 337 citations
Engineering · Materials Science · #2D Materials and Applications #Advancements in Semiconductor Devices and Circuit Design #CMOS #Computer science #Electrical engineering #Engineering #Graphene research and applications #Materials science #Nanotechnology #Optoelectronics #Physics #Scalability #Semiconductor #Very-large-scale integration

paper · doi:10.1109/ted.2015.2443039

published in IEEE Transactions on Electron Devices 62(11), 3459-3469 (Institute of Electrical and Electronics Engineers)

openalex publication_date 2015/09/15 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/29

Abstract

Two-dimensional (2D) crystal semiconductors, such as the well-known molybdenum disulfide (MoS2), are witnessing an explosion in research activities due to their apparent potential for various electronic and optoelectronic applications. In this paper, dissipative quantum transport simulations using nonequilibrium Green's function formalism are performed to rigorously evaluate the scalability and performance of monolayer/multilayer 2D semiconductor-based FETs for sub-10 nm gate length very large-scale integration (VLSI) technologies. Device design considerations in terms of the choice of prospective 2D material/structure/technology to fulfill sub-10 nm International Technology Roadmap for Semiconductors (ITRS) requirements are analyzed. First, it is found that MoS2FETs can meet high-performance (HP) requirement up to 6.6 nm gate length using bilayer MoS2as the channel material, while low-standby-power (LSTP) requirements present significant challenges for all sub-10 nm gate lengths. Second, by studying the effects of underlap (UL) structures, scattering strength, and carrier effective mass, it is found that the high mobility and suitably low effective mass of tungsten diselenide (WSe2), aided by the UL, enable 2D FETs for both HP and LSTP applications at the smallest foreseeable (5.9 nm) gate length. Finally, possible solutions for sub-5 nm gate lengths, specifically anisotropic 2D semiconductor materials for HP and sub-kT/q switch (2D tunnel FET) for LSTP, are also proposed based on the effects of critical material parameters on the device performance.

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