A Regular Layout for Parallel Adders

1982/03/01 by Brent, Kung · 1,145 citations
Computer Science · Engineering · Mathematics · #Adder #Arithmetic #Binary number #Chip #Computer hardware #Computer science #Embedded system #Latency (audio) #Low-power high-performance VLSI design #Mathematics #Measure (data warehouse) #Numerical Methods and Algorithms #Parallel computing #VLSI and FPGA Design Techniques #Very-large-scale integration

paper · doi:10.1109/tc.1982.1675982

published in IEEE Transactions on Computers C-31(3), 260-264 (Institute of Electrical and Electronics Engineers)

openalex publication_date 1982/03/01 · openalex created_date 2025/10/10 · openalex updated_date 2026/08/01

Abstract

With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.

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