Automatic Generation of System-Level Test for Un-Core Logic of Large Automotive SoC

2025/07/10 by Francesco Angione, Paolo Bernardi, Giusy Iaria +3
Computer Science · Engineering · #Algorithm #Automotive industry #Computer science #Embedded system #Engineering #Integrated Circuits and Semiconductor Failure Analysis #Logic gate #Logic synthesis #System on a chip #VLSI and Analog Circuit Testing #VLSI and FPGA Design Techniques

paper · doi:10.1109/tc.2025.3587515

openalex publication_date 2025/07/10 · openalex created_date 2025/10/10 · openalex updated_date 2026/08/01

Abstract

Traditional structural tests are powerful automatic approaches for capturing faulty behavior in integrated circuits. Besides the ease of generating test patterns, structural methods are known to be able to cover a vast but incomplete spectrum of all possible faults in a System-on-Chip (SoC). A new step in the manufacturing test flow has been added to fill the leftover gaps of structural tests, called the System-Level Test (SLT), which resembles the final workload, and environment.This work illustrates how to build up an automated generation engine to synthesize SLT programs that effectively attack structural test weaknesses from both a holistic and an analytical perspective. The methodology targets the crossbar module, as one of the most critical areas in the SoC, and it simultaneously creates a ripple effect across the un-core logic.Experimental results are conducted on an automotive SoC manufactured by STMicroelectronics.

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