Write Disturb in Ferroelectric FETs and Its Implication for 1T-FeFET AND Memory Arrays

2018/09/27 by Kai Ni, Xueqing Li, J. A. Smith +3 · 3 citations
Engineering · Materials Science · #Advanced Memory and Neural Computing #Ferroelectric and Negative Capacitance Devices #MXene and MAX Phase Materials

paper · doi:10.1109/led.2018.2872347

openalex publication_date 2018/09/27 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/29

Abstract

In this letter, the write disturb of Hf0.5Zr0.5O2-based 1T-FeFET nonvolatile AND memory array is experimentally investigated for VW/2 and VW/3 inhibition bias schemes to determine the worst-case memory sensing condition. Read margin analysis reveals that the increased leakage current in the low-VTHerased state and the increased read current of the high-VTHprogrammed state are the key factors that limit the maximum array size.

Citations

• Crossbar RRAM Arrays: Selector Device Requirements During Write Operation

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