Combined Integer and Variable Precision (CIVP) Floating Point Multiplication Architecture for FPGAs

2007/11/16 by Himanshu Thapliyal, Thapliyal, Himanshu, Hamid R. Arabnia +5
Computer Science · Engineering · #Digital Filter Design and Implementation #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Low-power high-performance VLSI design #Numerical Methods and Algorithms

paper · pdf · doi:10.48550/arxiv.0711.2671

openalex publication_date 2007/11/16 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28

Abstract

In this paper, we propose an architecture/methodology for making FPGAs suitable for integer as well as variable precision floating point multiplication. The proposed work will of great importance in applications which requires variable precision floating point multiplication such as multi-media processing applications. In the proposed architecture/methodology, we propose the replacement of existing 18x18 bit and 25x18 bit dedicated multipliers in FPGAs with dedicated 24x24 bit and 24x9 bit multipliers, respectively. We have proved that our approach of providing the dedicated 24x24 bit and 24x9 bit multipliers in FPGAs will make them efficient for performing integer as well as single precision, double precision, and Quadruple precision floating point multiplications.

Related

• On Approximate 8-bit Floating-Point Operations Using Integer Operations
• Customizing Number Representation and Precision
• A decimal floating-point accurate scalar product unit with a parallel fixed-point multiplier on a Virtex-5 FPGA
• Fast Arbitrary Precision Floating Point on FPGA
• Design and implementation of an out-of-order execution engine of floating-point arithmetic operations