2012/07/21 by Raja Jitendra Nayaka, Nayaka, Raja Jitendra, Rajashekhar C. Biradar +1
Computer Science · #Airccse Conferences #Embedded Systems Design Techniques #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Interconnection Networks and Systems #Network Packet Processing and Optimization #Networking and Internet Architecture (cs.NI)
paper · pdf · doi:10.48550/arxiv.1207.5138
openalex publication_date 2012/07/21 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
As the demand for Internet expands significantly in numbers of users, servers, IP addresses, switches and routers, the IP based network architecture must evolve and change. The design of domain specific processors that require high performance, low power and high degree of programmability is the bottleneck in many processor based applications. This paper describes the design of ethernet packet processor for system-on-chip (SoC) which performs all core packet processing functions, including segmentation and reassembly, packetization classification, route and queue management which will speedup switching/routing performance. Our design has been configured for use with multiple projects ttargeted to a commercial configurable logic device the system is designed to support 10/100/1000 links with a speed advantage. VHDL has been used to implement and simulated the required functions in FPGA.