2019/11/11 by Jacob T. Grycel, Grycel, Jacob T., Robert J. Walls +1
Computer Science · #Advanced Malware Detection Techniques #Chaos-based Image/Signal Encryption #Cryptographic Implementations and Security #Cryptography and Security (cs.CR) #FOS: Computer and information sciences #Hardware Architecture (cs.AR)
paper · pdf · doi:10.48550/arxiv.1911.04378
openalex publication_date 2019/11/11 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
Advanced Encryption Standard (AES) implementations on Field Programmable Gate\nArrays (FPGA) commonly focus on maximizing throughput at the cost of utilizing\nhigh volumes of FPGA slice logic. High resource usage limits systems' abilities\nto implement other functions (such as video processing or machine learning)\nthat may want to share the same FPGA resources. In this paper, we address the\nshared resource challenge by proposing and evaluating a low-area, but\nhigh-throughput, AES architecture. In contrast to existing work, our\nDSP/RAM-Based Low-CLB Usage (DRAB-LOCUS) architecture leverages block RAM tiles\nand Digital Signal Processing (DSP) slices to implement the AES Sub Bytes, Mix\nColumns, and Add Round Key sub-round transformations, reducing resource usage\nby a factor of 3 over traditional approaches. To achieve area-efficiency, we\nbuilt an inner-pipelined architecture using the internal registers of block RAM\ntiles and DSP slices. Our DRAB-LOCUS architecture features a 12-stage pipeline\ncapable of producing 7.055 Gbps of interleaved encrypted or decrypted data, and\nonly uses 909 Look Up tables, 593 Flip Flops, 16 block RAMs, and 18 DSP slices\nin the target device.\n