2009/01/01 by Bernadette Charron-Bost, Charron-Bost, Bernadette, Shlomi Dolev +5
Computer Science · #Cloud Computing and Resource Management #Distributed systems and fault tolerance #Fault-tolerant distributed algorithms #IoT and Edge/Fog Computing #VLSI systemson- chip #digital logic #fault tolerance #specifications #synchronous vs. asynchronous circuits
paper · doi:10.4230/dagsemproc.08371.2
openalex publication_date 2009/01/01 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
Chips was devoted to exploring whether the wealth of existing fault-tolerant distributed algorithms research can be utilized for meeting the challenges of future-generation VLSI chips. Participants from both the distributed fault-tolerant algorithms community, interested in this emerging application domain, and from the VLSI systems-on-chip and digital design community, interested in well-founded system-level approaches to fault-tolerance, surveyed the current state-of-the-art and tried to identify possibilities to work together. The seminar clearly achieved its purpose: It became apparent that most existing research in Distributed Algorithms is too heavy-weight for being immediately applied in the “core” VLSI design context, where power, area etc. are scarce resources. At the same time, however, it was recognized that emerging trends like large multicore chips and increasingly critical applications create new and promising application domains for fault-tolerant distributed algorithms. We are convinced that the very fruitful cross-community interactions that took place during the Dagstuhl seminar will contribute to new research activities in those areas.