2018/05/26 by Marie Nguyen, Nguyen, Marie, James C. Hoe +1 · 1 voice
Computer Science · Engineering · #CCD and CMOS Imaging Sensors #Embedded Systems Design Techniques #VLSI and Analog Circuit Testing #cs.AR
paper · pdf · doi:10.48550/arxiv.1805.10431
arxiv published 2018/05/26 · arxiv updated 2018/06/21
This paper presents an FPGA runtime framework that demonstrates the feasibility of using dynamic partial reconfiguration (DPR) for time-sharing an FPGA by multiple realtime computer vision pipelines. The presented time-sharing runtime framework manages an FPGA fabric that can be round-robin time-shared by different pipelines at the time scale of individual frames. In this new use-case, the challenge is to achieve useful performance despite high reconfiguration time. The paper describes the basic runtime support as well as four optimizations necessary to achieve realtime performance given the limitations of DPR on today's FPGAs. The paper provides a characterization of a working runtime framework prototype on a Xilinx ZC706 development board. The paper also reports the performance of realtime computer vision pipelines when time-shared.