2010/01/01 by Peter M. Athanas, Jürgen Becker, Athanas, Peter M. +5
Computer Science · #CAD Tool Support #Circuit Technologies #Computational Models #Dynamically Run-Time Reconfigurable Computing Architectures #Embedded Systems Design Techniques #Interconnection Networks and Systems #Parallel Computing and Optimization Techniques #Reconfigurable/Adaptive Computing based on Nanotechnologies #Self- adaptive Systems #System Architecture
paper · doi:10.4230/dagsemproc.10281.2
openalex publication_date 2010/01/01 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
Dynamic and partial reconfiguration of hardware architectures such as FPGAs and coarse grain processing arrays bring an additional level of flexibility in the design of electronic systems by exploiting the possibility of configuring functions on-demand during run-time. When compared to emerging software-programmable Multi-Processor System-on-a-Chip (MPSoC) solutions, they benefit a lot from lower cost, more dedication and fit to a certain problem class as well as power and area efficiency. This has led to many new ways of approaching existing research topics in the area of hardware design and optimization techniques. For example, the possibility of performing adaptation during run-time raises questions in the areas of dynamic control, real-time response, on-line power management and design complexity, since the reconfigurability increases the design space towards infinity.