CIMR-V: An End-to-End SRAM-based CIM Accelerator with RISC-V for AI Edge Device

2025/03/28 by Yan-Cheng Guo and, Tian‐Sheuan Chang, and, Yan-Cheng Guo +13
Computer Science · #Big Data and Digital Economy #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Network Packet Processing and Optimization #Parallel Computing and Optimization Techniques

paper · pdf · doi:10.48550/arxiv.2503.22072

openalex publication_date 2025/03/28 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28

Abstract

Computing-in-memory (CIM) is renowned in deep learning due to its high energy efficiency resulting from highly parallel computing with minimal data movement. However, current SRAM-based CIM designs suffer from long latency for loading weight or feature maps from DRAM for large AI models. Moreover, previous SRAM-based CIM architectures lack end-to-end model inference. To address these issues, this paper proposes CIMR-V, an end-to-end CIM accelerator with RISC-V that incorporates CIM layer fusion, convolution/max pooling pipeline, and weight fusion, resulting in an 85.14% reduction in latency for the keyword spotting model. Furthermore, the proposed CIM-type instructions facilitate end-to-end AI model inference and full stack flow, effectively synergizing the high energy efficiency of CIM and the high programmability of RISC-V. Implemented using TSMC 28nm technology, the proposed design achieves an energy efficiency of 3707.84 TOPS/W and 26.21 TOPS at 50 MHz.

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