2014/02/12 by Bei Yu, Yen-Hung Lin, Yu, Bei +10
Computer Science · Engineering · #Advancements in Photolithography Techniques #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Nanofabrication and Lithography Techniques #VLSI and Analog Circuit Testing #cs.AR
paper · pdf · doi:10.48550/arxiv.1402.2890
arxiv created 2014/02/12 · openalex publication_date 2014/02/12 · arxiv updated 2014/02/13 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
Triple patterning lithography (TPL) has received more and more attentions from industry as one of the leading candidate for 14nm/11nm nodes. In this paper, we propose a high performance layout decomposer for TPL. Density balancing is seamlessly integrated into all key steps in our TPL layout decomposition, including density-balanced semi-definite programming (SDP), density-based mapping, and density-balanced graph simplification. Our new TPL decomposer can obtain high performance even compared to previous state-of-the-art layout decomposers which are not balanced-density aware, e.g., by Yu et al. (ICCAD'11), Fang et al. (DAC'12), and Kuang et al. (DAC'13). Furthermore, the balanced-density version of our decomposer can provide more balanced density which leads to less edge placement error (EPE), while the conflict and stitch numbers are still very comparable to our non-balanced-density baseline.