2015/09/17 by Bo Wang, Wang, Bo, Kezhi Li +5
Computer Science · Engineering · #Advanced Electrical Measurement Techniques #Advancements in PLL and VCO Technologies #FOS: Computer and information sciences #Other Computer Science (cs.OH) #Sensor Technology and Measurement Systems #cs.OH
paper · pdf · doi:10.48550/arxiv.1509.05192
This paper has been withdrawn by the author due to the imperfection of the circuit, i.e., the long reset time of hundreds ns to several us
openalex publication_date 2015/09/17 · arxiv created 2016/05/10 · arxiv updated 2016/05/11 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
An all-digital comparator with full input range is presented. It outperforms the nowaday all-digital comparators with its large rail-to-rail input range. This is achieved by the proposed Yin-yang balance mechanism between the two logic gates: NAND3 and OAI (Or-And-Invert). The important design considerations to achieve this balance are presented, such as the driving strength manipulation and the use of pre-distortion technique. Constructed only by commercially available digital standard cells, the layout of the proposed comparator is generated automatically by standard digital Place & Route routine within several minutes. The Verilog code for the proposed circuit is given, and the circuit is successfully implemented in 130nm CMOS technology with the power consumption of 0.176mW at the clock of 330MHz.