2019/08/19 by Ning Qiao, Qiao, Ning, Giacomo Inidveri +1
Computer Science · Engineering · #Advanced Memory and Neural Computing #Artificial intelligence #Artificial neural network #Asynchronous communication #Computer architecture #Computer science #Digital electronics #Electrical engineering #Electronic circuit #Electronic engineering #Emerging Technologies (cs.ET) #Engineering #FOS: Computer and information sciences #Ferroelectric and Negative Capacitance Devices #Integrated circuit #Materials science #Mixed-signal integrated circuit #Monte Carlo method #Multi-core processor #Neuromorphic engineering #Optoelectronics #Parallel computing #Scaling #Semiconductor materials and devices #Silicon #Silicon on insulator #Telecommunications #cs.ET
paper · pdf · doi:10.48550/arxiv.1908.07411
published in arXiv (Cornell University) (Cornell University) · 2016 IEEE Biomedical Circuits and Systems Conference (BioCAS)
arxiv created 2019/08/19 · openalex publication_date 2019/08/19 · arxiv updated 2019/08/21 · openalex created_date 2019/08/29 · openalex updated_date 2026/07/28
As processes continue to scale aggressively, the design of deep sub-micron, mixed-signal design is becoming more and more challenging. In this paper we present an analysis of scaling multi-core mixed-signal neuromorphic processors to advanced 28 nm FD-SOI nodes. We address analog design issues which arise from the use of advanced process, including the problem of large leakage currents and device mismatch, and asynchronous digital design issues. We present the outcome of Monte Carlo Analysis and circuit simulations of neuromorphic sub threshold analog/digital neuron circuits which reproduce biologically plausible responses. We describe the AER used to implement PCHB based asynchronous QDI routing processes in multi-core neuromorphic architectures and validate their operation via circuit simulation results. Finally we describe the implementation of custom 28 nm CAM based memory resources utilized in these multi-core neuromorphic processor and discuss the possibility of increasing density by using advanced RRAM devices integrated in the 28 nm Fully-Depleted Silicon on Insulator (FD-SOI) process.