2025/06/11 by Nilesh Pandey, Dipanjan Basu, Pandey, Nilesh +3
Engineering · #Advancements in Semiconductor Devices and Circuit Design #Applied Physics (physics.app-ph) #FOS: Physical sciences #Ferroelectric and Negative Capacitance Devices #Semiconductor materials and devices
paper · pdf · doi:10.48550/arxiv.2506.09356
openalex publication_date 2025/06/11 · openalex created_date 2025/10/10 · openalex updated_date 2026/07/28
This paper presents the design and benchmarking of cryogenic bulk-FETs using an experimentally calibrated TCAD framework that integrates 2-D electrostatics and interface-trap effects from T = 2 K to 300 K. For a 28-nm node device, carrier transport is predominantly ballistic at T = 2 K and becomes quasi-ballistic as temperature increases. At cryogenic temperatures, higher interface-trap densities increase the effective threshold voltage and suppress subthreshold conduction. However, when the ON-state bias is adjusted to account for the trap-induced Vt shift, interface traps are found to worsen ION/IOFF along with degrading the subthreshold swing (SS) and reducing mobility across all temperatures. The spatial standard deviation σ of the trap distribution modulates these behaviors: highly localized traps (σ∼ 1--2 nm) exacerbate short-channel effects (SCEs), whereas broader, nearly uniform distributions (σ≥ 50 nm) elevate the entire barrier and suppress SCEs until saturation as σ→ Lg. The TCAD predictions closely match experimental data at 4.2 K, 77 K, and 300 K, providing design guidelines to optimize ION/IOFF, SS, mobility, and DIBL for cryogenic CMOS technology nodes.