2014/07/25 by Heechul Yun, Yun, Heechul
Computer Science · #Distributed #FOS: Computer and information sciences #Parallel #Performance (cs.PF) #and Cluster Computing (cs.DC) #cs.DC #cs.PF
paper · pdf · doi:10.48550/arxiv.1407.7448
Technical Report
arxiv created 2014/07/25 · arxiv updated 2014/07/29
In modern Commercial Off-The-Shelf (COTS) multicore systems, each core can generate many parallel memory requests at a time. The processing of these parallel requests in the DRAM controller greatly affects the memory interference delay experienced by running tasks on the platform. In this paper, we model a modern COTS multicore system which has a nonblocking last-level cache (LLC) and a DRAM controller that prioritizes reads over writes. To minimize interference, we focus on LLC and DRAM bank partitioned systems. Based on the model, we propose an analysis that computes a safe upper bound for the worst-case memory interference delay. We validated our analysis on a real COTS multicore platform with a set of carefully designed synthetic benchmarks as well as SPEC2006 benchmarks. Evaluation results show that our analysis is more accurately capture the worst-case memory interference delay and provides safer upper bounds compared to a recently proposed analysis which significantly under-estimate the delay.