Static extraction of memory access profiles for multi-core interference\n analysis of real-time tasks

2021/03/31 by Thomas Carle, Carle, Thomas, Hugues Cassé +1
Computer Science · #Distributed systems and fault tolerance #Embedded Systems Design Techniques #FOS: Electrical engineering #Real-Time Systems Scheduling #Systems and Control (eess.SY) #electronic engineering #information engineering

paper · pdf · doi:10.48550/arxiv.2103.17082

openalex publication_date 2021/03/31 · openalex created_date 2025/10/10 · openalex updated_date 2026/08/04

Abstract

We present a static analysis framework for real-time task systems running on\nmulti-core processors. Our method analyzes tasks in isolation at the binary\nlevel and generates worst-case timing and memory access profiles. These\nprofiles can then be combined to perform an interference analysis at the task\nsystem level, as part of a multi-core Worst-Case Response Time (WCRT) analysis.\nIn this paper we introduce a formal description of the models and algorithmic\nbuilding blocks composing our framework. We also discuss how the memory access\nprofiles generated by our method could be used to feed existing\nstate-of-the-art WCRT frameworks. To the best of our knowledge, it is the first\ntime that a method is documented on how to produce sound, safe and precise\ninputs for interference analysis methods.\n

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