2020/03/21 by Khanh N. Dang, Dang, Khanh N., Yuichi Okuyama +3 · 1 citation
Computer Science · Engineering · #Advanced Memory and Neural Computing #FOS: Computer and information sciences #Hardware Architecture (cs.AR) #Interconnection Networks and Systems #Radiation Effects in Electronics #cs.AR
paper · pdf · doi:10.48550/arxiv.2003.09616
arxiv created 2020/03/21 · openalex publication_date 2020/03/21 · arxiv updated 2020/03/24 · openalex created_date 2020/03/27 · openalex updated_date 2026/07/28
Network-on-Chip (NoC) paradigm has been proposed as an auspicious solution to handle the strict communication requirements between the increasingly large number of cores on a single multi and many-core chips. However, NoC systems are exposed to a variety of manufacturing, design and energetic particles factors making them vulnerable to permanent (hard) faults and transient (soft) errors. In this paper, we present a comprehensive soft error and hard fault tolerant 3D-NoC architecture, named 3D-Hard-Fault-Soft-Error-Tolerant-OASIS-NoC (3D-FETO). With the aid of adaptive algorithms, 3D-FETO is capable of detecting and recovering from soft errors occurring in the routing pipeline stages and is leveraging on reconfigurable components to handle permanent faults occurrence in links, input buffers, and crossbar. In-depth evaluation results show that the 3D-FETO system is able to work around different kinds of hard faults and soft errors while ensuring graceful performance degradation, minimizing the additional hardware complexity and remaining power-efficient.