2016/08/24 by Sourav Das, Janardhan Rao Doppa, Das, Sourav +5
Computer Science · Engineering · Materials Science · #Advancements in Battery Materials #Distributed #Emerging Technologies (cs.ET) #FOS: Computer and information sciences #Interconnection Networks and Systems #Networking and Internet Architecture (cs.NI) #Parallel #Supercapacitor Materials and Fabrication #and Cluster Computing (cs.DC)
paper · pdf · doi:10.48550/arxiv.1608.06972
openalex publication_date 2016/08/24 · openalex created_date 2022/10/01 · openalex updated_date 2026/07/28
A three-dimensional (3D) Network-on-Chip (NoC) enables the design of high\nperformance and low power many-core chips. Existing 3D NoCs are inadequate for\nmeeting the ever-increasing performance requirements of many-core processors\nsince they are simple extensions of regular 2D architectures and they do not\nfully exploit the advantages provided by 3D integration. Moreover, the\nanticipated performance gain of a 3D NoC-enabled many-core chip may be\ncompromised due to the potential failures of through-silicon-vias (TSVs) that\nare predominantly used as vertical interconnects in a 3D IC. To address these\nproblems, we propose a machine-learning-inspired predictive design methodology\nfor energy-efficient and reliable many-core architectures enabled by 3D\nintegration. We demonstrate that a small-world network-based 3D NoC (3D SWNoC)\nperforms significantly better than its 3D MESH-based counterparts. On average,\nthe 3D SWNoC shows 35% energy-delay-product (EDP) improvement over 3D MESH for\nthe PARSEC and SPLASH2 benchmarks considered in this work. To improve the\nreliability of 3D NoC, we propose a computationally efficient spare-vertical\nlink (sVL) allocation algorithm based on a state-space search formulation. Our\nresults show that the proposed sVL allocation algorithm can significantly\nimprove the reliability as well as the lifetime of 3D SWNoC.\n