Laser Processing For 3D Junctionless Transistor Fabrication

2020/11/30 by Bosch, D., Alba, P. Acosta, Kerdiles, S. +13
#Applied Physics (physics.app-ph) #FOS: Physical sciences

paper · doi:10.48550/arxiv.2011.15061

Abstract

To take fully advantage of Junctionless transistor (JLT) low-cost and low-temperature features we investigate a 475 degC process to create onto a wafer a thin poly-Si layer on insulator. We fabricated a 13nm doped (Phosphorous, 1E19 at/cm3) poly-silicon film featuring excellent roughness values (Rmax= 1.6nm and RMS=0.2nm). Guidelines for grain size optimization using nanosecond (ns) laser annealing are given.

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